The present invention relates to clock switching circuits generally and, more particularly, to a method and apparatus for switching clocks presented to synchronous static random access memories (SRAMS).
Synchronous SRAMs have an input clock that is used to time accesses to the RAM. The clock provides the timing requirements for address, data, and control signals with respect to setup, hold and access times. The clock is used internally to, among other things, latch address, data, and control inputs and to pre-charge internal nodes.
In a totally synchronous environment, all access to a synchronous SRAM comes from one or more agents running on a common system clock. The common system clock can be used as the input clock to the synchronous SRAM. In an asynchronous environment, agents run in different time domains. The input clock to the synchronous SRAM must be switched to the clock of the agent seeking access. Switching the input clock can cause problems (e.g., violations of the synchronous SRAM""s input clock timing requirements, glitches, and/or runt pulses). Violating input timing requirements, glitches, and/or runt pulses can result in loss of data, invalid data, and or a system hang.
Prior designs avoided such timing problems by using Asynchronous RAMs. Asynchronous RAMs do not require a clock input. However, synchronous SRAMs are desirable in many applications even though access would be required by agents running in different time domains.
A solution is needed for switching the input clock. and/or control signals of a synchronous SRAM without glitches, runt pulses, and/or timing violations.
The present invention concerns a method and apparatus for switching clocks comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate (i) a first signal in response toga select signal and a first clock signal, (ii) a second signal in response to the first signal and a second clock signal, (iii) a third signal in response to the select signal and the second clock signal, and (iv) a fourth signal in response to the third signal and the first clock signal. The second circuit may be configured to generate a first enable signal and a second enable signal in response to (i) the first signal, (ii) the second signal, (iii) the third signal, and (iv) the fourth signal. The third circuit may be configured to select (i) one or more first input signals, (ii) one or more second input signals, or (iii) a predetermined logic level as one or more output signals in response to the first enable signal and the second enable signal.
The objects, features and advantages of the present invention include providing a method and/or apparatus that may switch clocks presented to one or more memories (e.g., synchronous SRAMs) without (i) violating timing requirements, (ii) generating glitches, and/or (iii),generating runt pulses.